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APPLICATION NOTE
Omni
ision
TM
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Implementation Guide
Last Modified: 7 December 2004 Document Version: 1.1
Revision Number
1.0 1.1
Date
11/29/04 12/07/04 Initial Release
Revision
In Table 4-1 on page 21, changed last six entries under column "Gain."
This document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
OmniVision Technologies, Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. * Third-party brands, names, and trademarks are the property of their respective owners. Note:
The information contained in this document is considered proprietary to OmniVision Technologies, Inc. This information may be distributed only to individuals or organizations authorized by OmniVision Technologies, Inc. to receive said information. Individuals and/or organizations are not allowed to re-distribute said information.
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM
Omni
ision
00Table of Contents
Section 1, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Section 2, Image Sensor Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Resolution Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Section 3, Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 3.2 3.3 Array Control and Frame Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 Frame Generation (SXGA, VGA, and lower resolutions) . . . . . . . . . 10 Sync Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Frame Rate Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 3.3.2 3.3.3 3.4 3.5 3.6 3.4.1 Clock Prescalar (Timing Generator) . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Dummy Pixel Adjustment (Output Formatter) . . . . . . . . . . . . . . . . . . 12 Dummy Line Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Digital Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Strobe Flash Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RGB Raw Data Output Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Section 4, Analog Processing Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.1 4.1.2 4.2 4.2.1 4.2.2 Manual Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Automatic Gain Control (AGC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Automatic White Balance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Manual White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
White Balance Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Section 5, Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 5.2 5.3 5.4 5.5 5.6 5.7
2
Gamma Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.1 5.2.1 Gamma Slope Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Color Matrix Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Color Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Sharpness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Noise-Canceling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 White Pixel Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Digital Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Lens Shading Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Section 6, Output Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 6.2 Windowing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 6.2.2 6.2.3 6.2.4 ITU-656 Format Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Frame Rate Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Output Data MSB/LSB Swap Enable . . . . . . . . . . . . . . . . . . . . . . . . . 37 D[9:0] - PCLK Reference Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Section 7, Digital Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Section 8, Special Image Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Section 9, Preview Mode to Still Image Capture Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 Exposure Time and Gain Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Section 10, SCCB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1 Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1.1 10.1.2 10.1.3 Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Standby Mode Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Tri-state Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Section 11, Prototyping and Evaluation Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 OV9650EAA Prototyping Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2 OV9650ECX USB 2.0 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Section 12, Lens selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Section 13, OV9650 Bug List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Appendix A, Reference SCCB Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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00List of Figures
Figure 1-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 5-1 Figure 5-2 Figure 6-1 Figure 6-2
OV9650 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Manual Exposure Frame Drop Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Desired Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SXGA Strobe Flash Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VGA Strobe Flash Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 QVGA Strobe Flash Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Gamma Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Lens Shading Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Example of Windowing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MSB/LSB Output Data Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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00List of Tables
Table 2-1 Table 2-2 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 7-1 Table 8-1
OV9650 Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Resolution Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Frame Rate, Pixel Clock Rate, and Input Clock Rate (CLKRC=0x81, 4X PLL) . 11 Banding Filter Value (Input Clock Frequency = 12 MHz, 4X PLL). . . . . . . . . . . . . 16 AEC Convergence Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AEC Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Total Gain to Control Bit Correlation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AGC General Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AGC Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AGC Convergence Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AWB Red/Blue Balance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Related Registers and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Color Matrix Related Registers and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Color Matrix Related Registers and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Lens Shading Correction Registers and Parameters . . . . . . . . . . . . . . . . . . . . . . . 32 Output Formatting General Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RGB:555 and RGB:565 Output Format Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Windowing Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Output Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Special Image Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 10-1 SCCB Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 10-2 Device Control Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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1 Introduction
This general application note is provided as a brief overview of the settings required for programming the OV9650 CAMERACHIPTM. The Implementation Guide supplies the design engineer with quick-start tips for successful design solutions. The OV9650 Datasheet provides complete information on the features, pin descriptions, and registers of the OV9650. The Implementation Guide is intended to complement the OV9650 Datasheet with considerations for PCB layout, register configurations, and timing parameters for rapid product design and deployment.
1.1 Function Description
Figure 1-1 shows the functional block diagram of the OV9650 image sensor. The OV9650 includes:
* * * * * * * Image Sensor Array (1300 x 1028 resolution) Timing Generator Analog Processing Block Digital Signal Processor (DSP) Output Formatter Digital Video Port SCCB Interface OV9650 Functional Block Diagram
Figure 1-1
G Analog Processing R
MUX
A/D
DSP MUX B
A/D
Formatter
Video Port
D[9:0]
Column Sense Amp Row Select
Exposure/Gain Detect
White Balance Detect
Image Array (1300 x 1028) Registers
Clock
Video Timing Generator Exposure/Gain Control White Balance Control SCCB Interface
XVCLK1
HREF
PCLK
VSYNC RESET
PWDN SIO_C SIO_D
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Image Sensor Array
2 Image Sensor Array
The OV9650 CAMERACHIP has an active image array size of 1300 columns by 1028 rows (1,336,400 pixels). The pixel cells themselves are identical, but have RGB color filters arranged in a line-alternating BG/GR Bayer Pattern. The final YUV/YCbCr image uses this filter pattern to interpolate each pixel's BG or GR color from the light striking the cell directly, as well as from the light striking the surrounding cells. The 'Raw RGB' image does not have any image processing. Table 2-1 lists all OV9650 output formats.
Table 2-1. Device OV9650 Output Formats Format YUV/YCbCr GRB OV9650 RGB565 RGB555 Raw RGB Output 8 bits, 4:2:2 (Interpolated color) 8 bits, 4:2:2 (Interpolated color) 5-bit R, 6-bit G, 5-bit B 5-bit R, 5-bit G, 5-bit B 10/8 bits (Bayer filter color) Register COM7[2]=0 (0x12) COM7[2]=1 (0x12), COM7[0]=0, COM15[4]=0 (0x40) COM7[2]=1 (0x12), COM7[0] = 0, COM15[4]=1 (0x40), COM15[5]=0 COM7[2]=1 (0x12), COM7[0] = 0, COM15[4]=1 (0x40), COM15[5]=1 COM7[0]=1 (0x12), COM7[2] = 1
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2.1 Resolution Formats
The OV9650 CAMERACHIP supports SXGA (1280x1024), VGA (640x480), CIF (352x288), QVGA (320x240), QCIF(176x144), QQVGA (160x120) and QQCIF (88x72). The different register settings for different resolution formats are listed in Table 2-2.
Note: Contact your local OmniVision support engineer for OV9650 Reference SCCB settings. Sensor power-on default values are not the best settings for image quality.
Table 2-2. Resolution
Resolution Register Settings (Sheet 1 of 2) Register Address COM1 (0x04) COM3 (0x0C) COM4 (0x0D) Value 0x00 0x00 0x00 0x80 0x00 0x81 0x93 0x50 0x00 0x04 0x80 0x81 0x40 0x91 0x12 0x43 0x00 0x04 0x80 0x83 0x10 0x91 0x12 0x43 30 fps QVGA YUV mode 30 fps VGA YUV mode 15 fps SXGA YUV mode Description (12 MHz Input Clock, 4X PLL)
SXGA
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39) COM1 (0x04) COM3 (0x0C) COM4 (0x0D)
VGA
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39) COM1 (0x04) COM3 (0x0C) COM4 (0x0D)
QVGA
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39)
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Image Sensor Array
Table 2-2. Resolution
Resolution Register Settings (Sheet 2 of 2) Register Address COM1 (0x04) COM3 (0x0C) COM4 (0x0D) Value 0x24 0x04 0x80 0x83 0x10 0x91 0x12 0x43 0x00 0x04 0x80 0x83 0x20 0x91 0x12 0x43 0x00 0x04 0x80 0x87 0x08 0x91 0x12 0x43 0x24 0x04 0x80 0x87 0x08 0x91 0x12 0x43 30 fps QQCIF YUV mode 30 fps QCIF YUV mode 30 fps CIF YUV mode 30 fps QQVGA YUV mode Description (12 MHz Input Clock, 4X PLL)
QQVGA
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39) COM1 (0x04) COM3 (0x0C) COM4 (0x0D)
CIF
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39) COM1 (0x04) COM3 (0x0C) COM4 (0x0D)
QCIF
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39) COM1 (0x04) COM3 (0x0C) COM4 (0x0D)
QQCIF
CLKRC (0x11) COM7 (0x12) ADC (0x37) ACOM (0x38) OFON (0x39)
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3 Timing Generator
In general, the timing generator controls the following functions:
* * * * * Array Control and Frame Generation (SXGA, VGA, QVGA, QQVGA, CIF, QCIF and QQCIF outputs) Internal timing signal generation and distribution Frame Rate Timing Exposure Control External timing outputs (VSYNC, HREF/HSYNC, and PCLK)
3.1 Array Control and Frame Generation 3.1.1 Frame Generation (SXGA, VGA, and lower resolutions)
SXGA frame generation uses Progressive scanning of the array in which rows are sequentially read and transferred out to the APB. The 'Raw RGB' output preserves the Bayer Filter pattern, so odd rows follow the pattern (BG) and even rows follow the pattern (GR). Simple sub-sampling mode just skips every other two rows and every other two columns for VGA mode. The OV9650 has built-in VarioPixelTM technology to improve sub-sampled image resolution and reduce noise level. Down-scaling technology down-scales the output size. VGA, QVGA, QQVGA, CIF, QCIF, and QQCIF have the same view angle which cuts 6.25% of the vertical view and keeps the same horizontal view of SXGA.
3.2 Sync Signal Selection
The OV9650 CAMERACHIP supplies two output sync signals: VSYNC and HREF. The vertical sync (VSYNC) signal is output on pin D2. The horizontal reference signal (HREF) is output on pin E1. The HSYNC signal is available on pin E1 (shares with HREF) when register COM10[6] (0x15) value is set to "1". The VSYNC and HSYNC signals are continuous. The HREF signal is only valid when there is active output data. If there is no output data, the HREF signal will remain at either high or low, depending on the polarity selection. The HSYNC/VSYNC/HREF/PCLK polarity selection is controlled by register COM10[0,1,3,4] (0x15), respectively. Usually, an application uses the rising edge of PCLK to capture data when HREF is high. The OV9650 can encode horizontal and vertical sync information into data. Set register COM1[6] (0x04) high to enable the CCIR656 format. Refer to the OV9650 Datasheet for detailed signal timing information.
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Timing Generator
3.3 Frame Rate Timing
The OV9650 offers three methods of frame rate adjustment:
* * * Clock Prescalar (Timing Generator) Dummy Pixel Adjustment (Output Formatter) Dummy Line Adjustment
3.3.1 Clock Prescalar (Timing Generator)
OV9650 divides the input clock by 2 first. Setting register CLKRC[7] (0x11) high turns on the internal clock doubler. Register CLKRC[5:0] is the internal clock pre-scalar. By programming register CLKRC[5:0] (0x11), the frame rate and pixel rate can be divided by 1, 2, 3, 4, ... 64. The internal clock frequency, fINT CLK, can be expressed as follows: fINT CLK = fCLK x ((CLKRC[7] + 1) / 2) / (CLKRC[5:0] + 1) tINT CLK = tCLK x (CLKRC[5:0] + 1) / ((CLKRC[7] + 1) / 2) Table 3-1 shows the maximum frame rate and pixel clock (PCLK) for the given input clock rate (XCLK1). RGB raw pixel clock rate is half of YUV mode for the same frame rate and resolution.
Table 3-1. Frame Rate, Pixel Clock Rate, and Input Clock Rate (CLKRC=0x81, 4X PLL) Maximum Frame Rate (fps) 15 15 30 30 60 60 60 60 60 60 120 120 120 120 XCLK1 (MHz) 12 12a 12 12 12 12 12 12 12 12 12 12 12 12 PCLK (MHz) 24 48 12 24 6 12 3 6 12 24 6 12 3 6
Resolution/Mode SXGA/Raw RGB SXGA/YUV VGA/Raw RGB VGA/YUV QVGA/Raw RGB QVGA/YUV QQVGA/Raw RGB QQVGA/YUV CIF/Raw RGB CIF/YUV QCIF/Raw RGB QCIF/YUV QQCIF/Raw RGB QQCIF/YUV
a. CLKRC=0x80
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3.3.2 Dummy Pixel Adjustment (Output Formatter)
By inserting dummy pixels in each row's output, the frame rate can be changed while leaving the pixel rate unchanged (see Section 6.2.2).
3.3.3 Dummy Line Adjustment
By inserting dummy lines in each frame output, the frame rate can be changed while leaving the pixel rate unchanged (see Section 6.2.2).
3.4 Exposure Control
The OV9650 CAMERACHIP supports both automatic and manual exposure control modes. The exposure time is defined as the interval from the cell precharge to the end of the photo-induced current measurement and can be controlled manually or by using the AEC function. This exposure control uses a 'rolling' shutter as exposure time is set on a row-by-row basis rather than on a frame-by-frame basis. Exposure Time interval is defined as follows (15 fps in SXGA mode): tEXPOSURE = 2 x (1520 x tINT CLK) x AEC[15:0] where AEC[15:0] is defined as: AEC[15:0] = {MSB, LSB} = {AECHM[5:0] (0xA1), AECH[7:0] (0x10), COM1[1:0] (0x04)} Each bit in AEC[15:0] = tROW interval = 2 x (1520 x tINT CLK) Note that both the AEC and AGC functions are interactive so registers and functions may be common to both. Also, in general, the AEC is the primary control and will be adjusted before the AGC (the AGC acts to adjust and center the AEC). The algorithm used for the electronic exposure control is based on average luminance of the full, center-quarter, or center-half image. Each frame has digitally-generated averages (YUV for YUV mode or RGB for RGB mode) which are used to set the exposure time. The exposure is optimized for a "normal" scene that assumes the subject is well lit relative to the background. In situations where the image is not well lit, the AEC white/black ratio may be adjusted to suit the needs of the application.
3.4.1 Digital Exposure Control
3.4.1.1 Manual Exposure Control Mode The manual exposure control mode allows for the companion backend processor to control the OV9650 image exposure. The companion backend processor may write exposure values to CAMERACHIP register AECHM[5:0] (0xA1) (MSB), AECH[7:0] (0x10), and COM1[1:0] (0x04) (LSB) according to its corresponding Auto-Exposure Control (AEC) algorithm.
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The minimum allowable exposure value is 1 line. Exposure modes of less than 1 line may be used in special cases. The LSB signifies the 1 line exposure time. The exposure value data is 16-bits in length. If the exposure increment exceeds the Exposure Gap (SXGA - 15 lines max, VGA - 11 lines max, QVGA/QVGA - 3 lines max, CIF - 89 lines max, QCIF/QQCIF - 41 lines max), the next frame will appear over-exposed. Setting register COM9[1] (0x14) to a value of "1" will eliminate this over-exposure frame by eliminating the HREF signal output. This provision also allows for the companion backend processor to use the VSYNC as a frame data reset to eliminate the undesired frame by register COM9[2] (0x14). Refer to Figure 3-1 for details.
Figure 3-1 Manual Exposure Frame Drop Timing Diagram
Rolling Horizontal Band Elimination in Manual Mode The OV9650 supports a rolling shutter exposure mode and requires special exposure values when used in 50/60 Hz lighting conditions to eliminate rolling horizontal band (flicker). The minimum exposure value is 1/120 second for 60 Hz and 1/100 second for 50 Hz lighting conditions. The following steps outline how to calculate the proper exposure value at 50 Hz/60 Hz light conditions:
1. Calculate the CAMERACHIP Minimum Exposure Line (MEL): Line period is Tline = K x Tpclk = K/fpclk, while K is PCLK number in one line, Tpclk is PCLK period (sec) and fpclk is PCLK frequency (Hz). Tpclk = 1/fpclk. For example, for default 1280 x 1024 at 7.5 fps, K is 1520 x 2 in YUV mode and 1520 in RGB Raw Data mode. But YUV PCLK frequency is double that of RGB Raw Data mode with same Tline. For 60 Hz lighting: MEL = (1/120)/Tline = 1/(120 x K x Tpclk) = fpclk/(120 x K) For 50 Hz lighting: MEL = (1/100)/Tline = 1/(100 x K x Tpclk) = fpclk/(100 x K) Note: For calculating MEL, use the line period of QCIF for QQCIF resolution. For QQVGA, use the line period of QVGA.
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2. Set the CAMERACHIP Available Exposure Line (AEL): Suppose N is integer, N = 1,2,3... Available exposure line are: AEL = N x MEL where AEL should be equal or less than the maximum exposure line limitation based on different resolutions. 3. Convert AEL to binary, and then send 2 LSBs hex number to register COM1[1:0] (0x04) and 8 MSBs hex number to register AECH[7:0] (0x10) and 6 MSBs to register AECHM[5:0] (0xA1).
Maximum Exposure Line Limitation OV9650 maximum exposure line values are:
* * * * * * * SXGA - 1048 lines Register setting: {AECHM[5:0] (0xA1) = 0x01, AECH[7:0] (0x10) = 0x06, COM1[1:0] (0x04) = 0x00} VGA - 498 lines Register setting: {AECHM[5:0] (0xA1) = 0x00, AECH[7:0] (0x10) = 0x7C, COM1[1:0] (0x04) = 0x02} QVGA - 248 lines Register setting: {AECHM[5:0] (0xA1) = 0x00, AECH[7:0] (0x10) = 0x3E, COM1[1:0] (0x04) = 0x00} QQVGA - 248 lines Register setting: {AECHM[5:0] (0xA1) = 0x00, AECH[7:0] (0x10) = 0x3E, COM1[1:0] (0x04) = 0x00} CIF - 382 lines Register setting: {AECHM[5:0] (0xA1) = 0x00, AECH[7:0] (0x10) = 0x5F, COM1[1:0] (0x04) = 0x02} QQCIF - 190 lines Register setting: {AECHM[5:0] (0xA1) = 0x00, AECH[7:0] (0x10) = 0x2F, COM1[1:0] (0x04) = 0x02} QQCIF - 190 lines Register setting: {AECHM[5:0] (0xA1) = 0x00, AECH[7:0] (0x10) = 0x2F, COM1[1:0] (0x04) = 0x02}
3.4.1.2 Automatic Exposure Control Mode (AEC) The AEC function allows for the CAMERACHIP to adjust the exposure without external command or control. The registers AECHM[5:0] (0xA1), AECH[7:0] (0x10), and COM1[1:0] (0x04) are adjusted by the CAMERACHIP internal controls and cannot be overwritten by an external device. Auto-Exposure Control Enable Bit To enable the AEC function, set register COM8[0] (0x13) to "1". The AEC controls image luminance using registers AEW (0x24) and AEB (0x25). The register AEW (0x24) value indicates the high threshold value and register AEB (0x25) indicates the low threshold value. When the target image luminance average value (YAVG) is within the range specified by registers AEW (0x24) and AEB (0x25), the AEC keeps the image exposure. When YAVG, is greater than the value in register AEW (0x24), the AEC will decrease the image exposure. When YAVG is less than the value in register AEB (0x25), the AEC will increase the image exposure. Accordingly, the value in register AEW (0x24) should be greater than the value in register AEB (0x25). The gap between the AEW (0x24) and AEB (0x25) register values controls the image stability. The recommended values for register AEW (0x24) and AEB (0x25) are: AEW (0x24) = 0x74; AEB (0x25) = 0x68.
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Rolling Horizontal Band Elimination in Auto Mode OV9650 also provides rolling horizontal band eliminate function in auto exposure mode. A banding filter is employed to eliminate banding caused by 50/60 Hz lighting. To enable this function, set register COM8[5] (0x13) to high. When the banding filter is enabled, the AEC will set the exposure time to a set of discete values, among which the minimum value is called the Banding Filter Value. OV9650 has two options to set the Banding Filter Value. The first option is manual banding filter mode, which is enabled by setting register COM11[0] (0x3B) to high. In manual banding filter mode, the Banding Filter Value is specified by register MBD[7:0] (0x6A) and the companion backend processor can program this register according to the lighting frequency. The second option is auto banding mode, which is enabled by setting register COM11[0] (0x3B) to low. In auto banding mode, the Banding Filter Value is specified by register BD50ST[7:0] (0xA2) if register COM17[0] (0x42) is high, or by register BD60ST[7:0] (0xA3) if register COM17[0] (0x42) is low. The companion backend processor can set register BD50ST[7:0] (0xA2) and BD60ST[7:0] (0xA3) for 50 Hz and 60 Hz, respectively, and then, toggle register COM17[0] (0x42) to switch between 50 Hz and 60 Hz lighting frequency. If the light is too strong, the minimum exposure time (equal to Banding Filter Value) to eliminate the banding may result in an over-exposed image. To avoid over-exposure, OV9650 has an option to allow the real exposure time to be less than the Banding Filter Value by setting register COM9[3] (0x14). Banding Filter Value Calculation The Banding Filter Value depends on the lighting frequency, frame rate, and maximum exposure. The equations are shown below. Frame rate can be derived from Table 3-1. Refer to section Maximum Exposure Line Limitation for the maximum exposure. Banding Filter Value = Frame Rate x Maximum Exposure Line 120 Frame Rate x Maximum Exposure Line 100 for 60 Hz
Banding Filter Value = Note:
for 50 Hz
1. Refer to "Maximum Exposure Line Limitation" on page 14 for details of maximum exposure line. 2. If the frame rate is adjusted by inserting dummy lines, the Maximum Exposure Line is equal to the original value plus the number of dummy lines. Consequently, the Banding Filter Value does not change with the number of dummy line. 3. If the frame rate is adjusted by inserting dummy pixels, the Maximum Exposure Line does not change. Consequently, the Banding Filter Value will change with the number of dummy pixels. In the case where the OV9650 works at a system clock frequency other than 24 MHz or 48 MHz, it is very convenient to adjust the frame rate by adding some dummy pixels (setting register EXHCH (0x2A) and EXHCL (0x2B)) while keep the Banding Filter Value the same with that using a 24 MHz or 48MHz system clock.
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Table 3-2 shows the Banding Filter Values for 50 Hz and 60 Hz light frequency conditions. Contact your local OmniVision FAE to get the appropriate setting for your application.
Table 3-2. Banding Filter Value (Input Clock Frequency = 12 MHz, 4X PLL) Banding Filter Value Resolution Clock Pre-Scalar (CLKRC (0x11)) Format YUV Raw YUV/Raw YUV/Raw YUV/Raw YUV/Raw YUV/Raw YUV/Raw Frame Rate (fps) 7.5 15 15 30 30 30 30 30 50 Hz (BD50ST (0xA2)) 0x4E 0x9D 0x4B 0x4B 0x4B 0x73 0x39 0x39 60 Hz (BD60ST (0xA3)) 0x41 0x83 0x3E 0x3E 0x3E 0x60 0x30 0x30
SXGA VGA QVGA QQVGA CIF QCIF QQCIF
0x81 0x83 0x83 0x83 0x83 0x87 0x87
With Banding Filter Disabled The AEC function supports both normal and fast speed selections in order to bring the image exposure into the range set by the values in registers AEW (0x24) and AEB (0x25). AEC set to normal mode will allow for single-step increase or decrease in the image exposure to maintain the specified range. AEC set to fast mode will provide for an approximate ten-step increase or decrease in the image exposure to maintain the specified range. A value of "0" in register COM8[7] (0x13) will result in normal speed operation and a "1" will result in fast speed operation. In fast mode, register VPT (0x26) sets the AEC control zone and register COM8[6] (0x13) sets the step size. When COM8[6]=1, the exposure time will decrease by half if the target image YAVG is greater than VPT[7:4] (0x26) x 16 and the exposure time will double if YAVG is less than VPT[3:0] (0x26) x 16. When COM8[6]=0, the exposure time will increase/decrease by 1/16th.
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AEC Convergence Limits Table 3-3 lists the registers used for setting AEC convergence limits.
Table 3-3. AEC Convergence Limits Function Control Zone - Upper Limit high nibble Control Zone - Lower Limit high nibble Stable Operating Region - Upper Limit Stable Operating Region - Lower Limit Step Size Limit Register VPT[7:4] VPT[3:0] AEW[7:0] AEB[7:0] COM8[6] Address 0x26 0x26 0x24 0x25 0x13
As shown in Figure 3-2, the AEC/AGC convergence uses two regions, the inner stable operating region and the outer Control Zone, which defines the convergence step size change as follows:
* Outside Control Zone Exposure time increase: 2 x (AEC[15:0]) Exposure time decrease: (AEC[15:0]) / 2 Inside Control Zone Exposure time increase: (AEC[15:0]) / 16 Exposure time decrease: (AEC[15:0]) / 16
*
Once the current value is inside the stable operating region, the AEC/AGC value has converged.
Figure 3-2 Desired Convergence
Desired Convergence
Control Zone
Stable Operating Region
Control Zone Upper Limit: {VPT[7:4] (0x26) (MSB), 4'b0000 (LSB)} Control Zone Lower Limit: {VPT[3:0] (0x26) (MSB), 4'b0000 (LSB)} Stable Operating Region Upper Limit: AEW[7:0] (0x24) Stable Operating Region Lower Limit: AEB[7:0] (0x25)
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AEC Options Table 3-4 shows lists the registers used for various AEC options.
Table 3-4. AEC Options Function Center-Based Reference Area Enable Banding Filter Enable Manual Banding Filter Enable Manual Banding Filter Value Auto Banding Filter Enable Auto Banding Filter Value Register Address 00: 01: 10: 11: Description Full Center-half Center-quarter Not allowed
COM11[4:3]
0x3B
COM8[5] COM11[0] MBD[7:0] COM11[0] BD50ST[7:0] BD60ST[7:0] COM17[0]
0x13 0x3B 0x6A 0x3B 0xA2 0xA3 0x42
Banding filter enable "1" High enable Minimum banding filter exposure time COM11[0]=0 Minimum banding filter exposure time 0: Select BD60ST[7:0] (0xA3) as Auto Banding Filter Value 1: Select BD50ST[7:0] (0xA2) as Auto Banding Filter Value 0: Exposure time CANNOT be less than Banding Filter Value 1: Exposure time CAN be less than Banding Filter Value
Auto Banding Filter Value Selection
Banding Filter - Avoid Over-Exposure
COM9[3]
0x14
Center-Based Reference Area Enable
Enabling this option changes the AEC/AGC exposure reference from the full array to the center-quarter, or center-half of the array.
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3.5 Strobe Flash Control
To achieve the best image quality possible in low light conditions, the use of a strobe flash is recommended. The OV9650 supports rolling shutter exposure mode. To avoid the need for a mechanical shutter, the OV9650 should be set to rolling shutter mode. When the rolling shutter mode is enabled and the image requires strobe flash illumination, the strobe timing must be limited. Timing diagrams for strobe flash timing are shown in Figure 3-4 and Figure 3-5.
Figure 3-3 SXGA Strobe Flash Timing Diagram
4 x Tline 9 x Tline VSYNC 12 x Tline
Line Output
0
1
2
1023 1024
0
0
1
2
1023 1024
Exposure Time ~= 1 Tframe Line Reset
0 1 2 1023 1024 0 0 1 2 1023
Note: If using live video mode for still capture and if flash is required, use maximum exposure (1 frame) and turn on flash only between this gray period.
Figure 3-4
VGA Strobe Flash Timing Diagram
4 x Tline 5 x Tline
VSYNC
8 x Tline
Line Output
0
1
2
479
480
0
0
1
2
479
480
Exposure Time ~= 1 Tframe Line Reset
0 1 2 479 480 0 0 1 2 479
Note: If using live video mode for still capture and if flash is required, use maximum exposure (1 frame) and turn on flash only between this gray period.
Figure 3-5
QVGA Strobe Flash Timing Diagram
2 x Tline
VSYNC
7 x Tline
Line Output
0
1
2
239
240
0
0
1
2
239
240
Exposure Time ~= 1 Tframe Line Reset
0 1 2 239 240 0 0 1 2 239
Note: If using live video mode for still capture and if flash is required, use maximum exposure (1 frame) and turn on flash only between this gray period.
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3.6 RGB Raw Data Output Sequence
Review the OV9650 Datasheet for complete details regarding the RGB raw data output. Register COM10[4] (0x15) determines when the data is valid. Setting register COM10[4] (0x15) t0 "1" indicates the data is updated at the rising edge and valid at the falling edge of PCLK. Setting register COM10[4] (0x15) t0 "0" indicates the data is updated at the falling edge and valid at the rising edge of PCLK. The data receiver should latch data when data is valid, with either the rising or falling edge of PCLK, depending on register COM10[4] (0x15). Depending on this polarity selection, if the HREF signal is high, the data is valid. If the HREF signal is low, the data is not valid. HREF polarity can also be changed by setting register COM10[3] (0x15). When using the HSYNC signal, adjust registers EXHCH (0x2A), HSYST (0x30), and HSYEN (0x31) to adjust the HSYNC signal rising and falling edges to obtain valid data. To obtain the HSYNC and HREF width, set registers HSTART (0x17) and HSTOP (0x18) or EXHCH (0x2A), HSYST (0x30), and HSYEN (0x31), respectively.
4 Analog Processing Block
This block performs all analog image functions including Automatic Gain Control (AGC), Automatic White Balance (AWB), and other image manipulation functions
4.1 Gain Control
The OV9650 CAMERACHIP provides support for both AGC and manual gain control modes.
4.1.1 Manual Gain Control
The manual gain control mode allows for the companion backend processor to control the OV9650 gain value. The companion backend processor may write gain control values to the CAMERACHIP RGB raw data register GAIN[7:0] (0x00) according to its corresponding AGC algorithm. The gain value is shown in Table 4-1.
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Table 4-1.
Total Gain to Control Bit Correlation Gain 1 1 + 1/16 1 + 2/16 1 + 3/16 1 + 4/16 1 + 5/16 1 + 6/16 1 + 7/16 1 + 8/16 1 + 9/16 1 + 10/16 1 + 11/16 1 + 12/16 1 + 13/16 1 + 14/16 1 + 15/16 2 x (1 + 0/16) 4 x (1 + 0/16) 8 x (1 + 0/16) 16 x (1 + 0/16) 32 x (1 + 0/16) 64 x (1 + 0/16) 64 x (1 + 15/16) dB 0 .375 .75 1.125 1.5 1.875 2.25 2.625 3 3.375 3.75 4.125 4.5 4.875 5.25 5.625 6 12 18 24 30 36 ~42
Registers VREF[7:6] (0x03), GAIN[7:0] (0x00) 00 00000000 00 00000001 00 00000010 00 00000011 00 00000100 00 00000101 00 00000110 00 00000111 00 00001000 00 00001001 00 00001010 00 00001011 00 00001100 00 00001101 00 00001110 00 00001111 00 00010000 00 00110000 00 01110000 00 11110000 01 11110000 11 11110000 11 11111111
Note: To achieve the best image quality, using "maximum" exposure and "minimum" gain for the highest S/N ratio is recommended. When operating in low-light condition, use the strobe flash.
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4.1.2 Automatic Gain Control (AGC)
The AGC function allows the CAMERACHIP to adjust image luminance and target level gain without external command or control. Register setting COM8[2] (0x13) enables AGC. The target level control registers are AEW (0x24) and AEB (0x25). Refer to Section 3.4.1.2 for additional details regarding the target level controls. When operating in fast AEC/AGC mode, use register VPT[7:0] (0x26) to set the conditions for fast AGC. Table 4-2 shows the general controls for the AGC.
Table 4-2. AGC General Controls Function AGC Enable Gain Setting Register COM8[2] VREF[7:6] GAIN[7:0] COM9[6:4] 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 128x 0x13 0x03 0x00 Address
Gain Ceiling Select
0x14
The analog pixel data first arrives at the AGC amplifier which can be automatically controlled by the AGC circuit or manually programmed by the user (see Table 4-3). In both cases, the gain control is active but when AGC is disabled, the gain setting is generated by the user and not updated by the AGC circuit.
Table 4-3. AGC Enable Bit AGC Status Enabled Disabled VREF[7:6] (0x03), GAIN[7:0] (0x00) Controlled by AGC Controlled by user
COM8[2] (0x13) 1 0
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The AGC operation is identical to the AEC (see Section 3.4.1.2). Table 4-4 lists the registers used to set the AGC convergence limits.
Table 4-4. AGC Convergence Limits Function Control Zone - Upper Limit high nibble Control Zone - Lower Limit high nibble Stable Operating Region - Upper Limit Stable Operating Region - Lower Limit Step Size Limit Register VPT[7:4] VPT[3:0] AEW[7:0] AEB[7:0] COM8[6] 0x26 0x26 0x24 0x25 0x13 Address
4.1.2.1 Center-Based Reference Area Enable Enabling this option changes the AEC/AGC exposure reference from the whole image to the center-quarter, or center-half of the array (set in the AEC section - see Section 3.4.1.2).
4.2 White Balance Control
The OV9650 CAMERACHIP supports auto/manual white balance control. After the initial pixel level adjustment, the Red and Blue channel gains are optimized to the Green channel to set the white balance. This white balance is either automatically-controlled by the AWB circuit or manually-controlled by the user. The following describes these AWB modes:
* * * Full user control - RED/BLUE channels are set manually Normal AWB control - RED/BLUE channels are under AWB control based on R/G/B average values Advanced AWB control - RED/BLUE channels are under AWB control based on color temperature
Register COM8[1] (0x13) enables the AWB function. If this bit is set low, the user can manually control red and blue gain. If this bit is set to high, the red and blue gain is controlled by the sensor's internal AWB algorithm.
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4.2.1 Automatic White Balance Control
In general, the white balance is done by adjusting the Red/Blue gain to match the Green channel. The Red/Blue data is first amplified by a fixed pre-gain and then sent to the two (Red and Blue) AWB-controlled amplifiers (see Table 4-5).
Table 4-5. AWB Red/Blue Balance Control Function Blue Channel Preamplifier Gain Setting Red Channel Preamplifier Gain Setting Red Channel Gain Setting Blue Channel Gain Setting Register HV[7:6] HV[5:4] RED[7:0] BLUE[7:0] 0x69 0x69 0x02 0x01 Address
Contact your local OmniVision FAE for advanced AWB settings.
4.2.2 Manual White Balance
In manual mode, the companion backend processor can control OV9650 internal Red and Blue register values to achieve white balance. These registers are BLUE (0x01) and RED (0x02) and are defined as follows:
* * Blue Gain: BLUE[7:0] (0x01) Red Gain: RED[7:0] (0x02)
Gain = [40 + ([7] x 80 + [6] x 47 + [5] x 25 + [4] x 13 + [3] x 7 + [2] x 4 + [1] x 2 + [0] x 1)] / 120 Blue and Red pre-gain are controlled by register HV[7:6] (0x69) and HV[5:4], respectively. The pre-gain is defined below:
* * Blue Pre-Gain = 1 + [7] x 0.50 + [6] x 0.25 Red Pre-Gain = 1 + [5] x 0.50 + [4] x 0.25
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Digital Signal Processor (DSP)
5 Digital Signal Processor (DSP)
The following subsections describe the controls for gamma, color matrix, and sharpness.
5.1 Gamma Control
The OV9650 gamma curve is composed of approximately 16 linear lines as shown in Figure 5-1 and Table 5-1.
Figure 5-1 Gamma Curve
255 GST15 GST14
GSP16 GSP15
GST3 GST2 GST1 GSP3 GSP2 GSP1 0 XREF1 XREF2 XREF3 XREF14 XREF15 255
Table 5-1.
Related Registers and Parameters (Sheet 1 of 2) Gamma Slope Name GSP1 Register 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 Horizontal Reference Name XREF1 XREF2 XREF3 XREF4 XREF5 XREF6 XREF7 4 8 16 32 40 48 56
25
Gamma Start Point Name Register
Value
GST1 GST2 GST3 GST4 GST5 GST6
0x7C 0x7D 0x7E 0x7F 0x80 0x81
GSP2 GSP3 GSP4 GSP5 GSP6 GSP7
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 5-1. Related Registers and Parameters (Sheet 2 of 2) Gamma Slope Name GSP8 GSP9 GSP10 GSP11 GSP12 GSP13 GSP14 GSP15 GSP16 Register 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B
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Gamma Start Point Name GST7 GST8 GST9 GST10 GST11 GST12 GST13 GST14 GST15 Register 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A
Horizontal Reference Name XREF8 XREF9 XREF10 XREF11 XREF12 XREF13 XREF14 XREF15 64 72 80 96 112 144 176 208 Value
5.1.1 Gamma Slope Calculation
The Gamma Slope is determined by following equation: Gamma Slope(i) = GST(i) - GST(i-1) XREF(i) -XREF(i-1)
Note: GST(0) =0, GST(16) = 255, XREF(0) =0, XREF(16) = 255.
To normalize the real number (Gamma Slope) to an 8-bit decimal value, the OV9650 applies 64 as a normalize factor as shown below: GSP (i) = Gamma Slope(i) x 64 = GST(i) - GST(i-1) XREF(i) -XREF(i-1) x 64
Note: Gamma Start Point and Slope should be matched; otherwise, there will be discontinuous points in the Gamma curve.
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5.2 Color Matrix
The color matrix is used to eliminate the cross talk induced by the micro-lens and color filter process. It also compensates for lighting and temperature effects. It also can be implemented for hue, color saturation, color space conversion from RGB to YUV or RGB to YCbCr.
5.2.1 Color Matrix Control
OV9650 has a 3x3 color matrix circuit inside. This color matrix performs the color correction and the RGB to YUV/YCbCr conversion. Also, because of the Matrix linear algebra characteristic, it can also do color gain and hue control as shown below: [YUV] = [Gain Matrix] x [Hue Matrix] x [RGB to YUV/YCbCr Matrix] x [Color correction] x [RGB] [YUV] = [Combined Matrix] [RGB]
Table 5-2. Color Matrix Related Registers and Parameters Name MTX1 MTX2 MTX3 MTX4 MTX5 MTX6 MTX7 MTX8 MTX9 SIGN SIGN ENABLE MTX1 MTX2 MTX3 MTX4 MTX5 MTX6 MTX7 MTX8 MTX9 MTXS[7:0] for MTX9 through MTX2, respectively HV[0] for MTX1 COM13[4] 0: Disable Matrix 1: Enable Matrix COM16[1] 0: Directly use Matrix 1: Double Matrix Register Address 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x69 0x3D
DOUBLER
0x41
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Each matrix component has 9-bits(1-bit sign and 8-bit data). This 3x3 matrix can be described as shown below: M1 M2 M3 M4 M5 M6 M7 M8 M9 And, the sign is assigned as shown below: HV[0] MTXS[0] MTXS[1] MTXS[2] MTXS[3] MTXS[4] MTXS[5] MTXS[6] MTXS[7] (0x69) (0x58) (0x58) (0x58) (0x58) (0x58) (0x58) (0x58) (0x58) sign bit of the MTX1 sign bit of the MTX2 sign bit of the MTX3 sign bit of the MTX4 sign bit of the MTX5 sign bit of the MTX6 sign bit of the MTX7 sign bit of the MTX8 sign bit of the MTX9
5.2.1.1 Color Correction Matrix Below is the OV9650 color correction matrix:
1.43 -0.24 -0.05 -0.36 1.38 -0.66 -0.07 -0.14 1.71
5.2.1.2 RGB to YUV conversion Matrix Below is the OV9650 RGB to YUV conversion matrix.
5 /16 -5 /16 11/16 9/16 -9/16 -9/16 2/16 14/16 -2/16
5.2.1.3 Hue Control
1 0 0 0 cos sin 0 sin -cos
5.2.1.4 Color Saturation
1 0 0 0 Gain 0 0 0 Gain
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Digital Signal Processor (DSP)
5.2.1.5 Final Matrix In OV9650, the M1M2M3 and M7M8M9 is swapped in YUV and RGB mode as shown below: In YUV output mode:
* * * Y'=r*M7+g*M8+b*M9 U'=r*M4+g*M5+b*M6 V'=r*M1+g*M2+b*M3
In RGB output mode:
* * * R'=r*M1+g*M2+b*M3 G'=r*M4+g*M5+b*M6 B'=r*M7+g*M8+b*M9
YUV Derivation from RGB:
* * * Y: 0.59G + 0.31R + 0.11B U: B - Y V: R - Y
YCbCr Derivation from RGB:
* * * Y: Cb: Cr: 0.59G + 0.31R + 0.11B 0.563 (B - Y) 0.713 (R - Y)
B&W Derivation from RGB:
* Y Channel
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5.3 Sharpness Control
The OV9650 features digital sharpness enhancement. It detects edge first and then, amplifies the edge difference only.
Table 5-3. Color Matrix Related Registers and Parameters Function Sharpness Enable Edge Detect Threshold Edge Enhancement Double Edge Enhancement Register COM14[1] COM22[7:6], EDGE[7:4] EDGE[3:0] COM14[0] Address 0x3E 0x8C 0x3F 0x3F 0x3E Active high 00 0000 is minimum threshold 0000 is minimum enhancement Active high Note
5.4 Noise-Canceling
The OV9650 has a built-in noise-canceling circuit to reduce noise. Setting register COM22[5] (0x8C) to high enables the noise-canceling function.
5.5 White Pixel Correction
The OV9650 has a built-in white pixel correction circuit. Setting register COM22[1:0] (0x8C) to "11" enables the white pixel correction function.
5.6 Digital Black Level Calibration
The OV9650 calibrates black level automatically. Setting register TSLB[0] (0x3A) to high enables black level calibration function.
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Digital Signal Processor (DSP)
5.7 Lens Shading Correction
Because of the non-uniform light transparence, the outer areas of the image appears darker than the center area. The lens correction function amplifies the outer areas of the image to obtain a uniform image.
Figure 5-2 Lens Shading Correction
Center area of image
LCC1[6:0] (0x62), LCC2[6:0] (0x63)
LCC2[7] = 1 (0x63)
LCC1[7] = 1 (0x62) LCC2[7] = 0 (0x63)
LCC1[7] = 0 (0x62)
Outer area of image
r
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 5-4. Lens Shading Correction Registers and Parameters Function Lens Correction Center Coordinates X Default LC_XY = (X,Y) = (0,0) Lens Correction Center Coordinates Y Default LC_XY = (X,Y) = (0,0) Radius of the circular section where lens correction is not needed Green Gain Parameter/ 3-channel (R, G and B) Gain Parameter LCC1[6:0] LCC1[7] 0: Offset LCC1[6:0] to +X direction 1: Offset LCC1[6:0] to -X direction LCC2[6:0] LCC2[7] 0: Offset LCC2[6:0] to +Y direction 1: Offset LCC2[6:0] to -Y direction LCC4 0x63 0x62 Register Address
Omni
ision
Note Lens Correction Center Coordinates X, one bit equals one pixel in full resolution. Lens Correction Center Coordinates Y, one bit equals one line in full resolution.
0x65 Green gain parameter if LCC5[2] = 1; Gain parameter for R,G,B channels if LCC5[2] = 0
LCC3 LCC5[2] 0: Use register LCC3 for gain parameter for R, G, and B channels 1: Use register LCC3 for Green Gain parameter, LCCFB for Blue Gain parameter, and LCCFR for Red Gain parameter LCC5[0] 0: Disable lens correction 1: Enable lens correction
0x64
Multi-Gain Control
0x66
Blue Gain Parameter Red Gain Parameter
LCCFB LCCFR
0x9D 0x9E
Not used if LCC5[2] = 0 Not used if LCC5[2] = 0
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Output Formatter
6 Output Formatter
This block controls all output and data formatting required prior to sending the image out on D[9:0]. Table 6-1 lists the control registers for the Output Formatting functions.
Table 6-1. Output Formatting General Controls Function Mirror Image Enable Vertical Flip Enable YUV/YCbCr Mode Raw RGB GRB 4:2:2 RGB Mode RGB:565 RGB:555 MVFP[5] MVFP[4] COM7[2] = 0 COM7[2] = 1, COM7[0] = 1 COM7[2] = 1,COM7[0] = 0, COM15[4] = 0 COM7[2] = 1,COM7[0] = 0, COM15[5] = 0, COM15[4] = 1 COM7[2] = 1, COM7[0] = 0, COM15[5] = 1, COM15[4] = 1 Register Address 0x1E 0x1E 0x12 0x12 0x12, 0x40 0x12, 0x40 0x12, 0x40
RGB:565 and RGB:555 are alternate output formats where each color is represented by different D[9:2] bit widths (see Table 6-2).
Table 6-2. RGB:555 and RGB:565 Output Format Controls D[9:2] Format RGB:565 RGB:555 Red RRRR Rxxx RRRR Rxxx Green GGGG GGxx GGGG Gxxx Blue BBBB Bxxx BBBB Bxxx
This format uses an odd/even byte pair to express the color for each pixel:
* RGB:565 Bytes Even Odd * RGB:555 Bytes Even Odd D9 00 G5 D8 R7 G4 D7 R6 G3 D6 R5 B7 D5 R4 B6 D4 R3 B5 D3 G7 B4 D2 G6 B3 D9 R7 G4 D8 R6 G3 D7 R5 G2 D6 R4 B7 D5 R3 B6 D4 G7 B5 D3 G6 B4 D2 G5 B3
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6.1 Windowing
The OV9650 CAMERACHIP windowing feature allows the users to define the active pixels used in the final image (frame) as required for low-resolution applications. Selecting the Start/Stop Row/Column addresses (modifying window size and/or position) does not change the frame or data rate. When windowing is enabled, the HREF signal is asserted to be consistent with the programmed 'active' horizontal and vertical region. Table 6-3 lists the control registers
Table 6-3. Windowing Control Registers Function Horizontal Frame (HREF Column) Start Horizontal Frame (HREF Column) Stop Vertical Frame (Row) Start Vertical Frame (Row) Stop Register HSTART[7:0] HREF[2:0] HSTOP[7:0] HREF[5:3] VSTRT[7:0] VREF[2:0] VSTOP[7:0] VREF[5:3] 0x17 0x32 0x18 0x32 0x19 0x03 0x1A 0x03 Address
Figure 6-1 shows an example of a windowed frame.
Figure 6-1 Example of Windowing
Selected Frame Data (120 Rows) HREF Selected Columns
Row Data #120 (160 Columns)
Selected Rows
Selected Frame
1028 Rows
1280 Columns
NOTE: The default output window is 1280 x 1028.
OV9650 windowing function can be implemented with the sub-sampling mode for the camera zoom function. For example, if the preview image size is 160 x 120 (QQVGA), the camera can be set to output QQVGA sub-sampling mode, then set to output QVGA mode (320 x 240) and use the windowing function to capture center-quarter area (160 x 120) to implement the 2x zoom-in function. Then, the camera can be set to VGA mode (640 x 480) or SXGA (1280 x 1028) mode, to implement 4x and 8x zoom-in function.
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6.2 Data Formatting
Table 6-4 lists the registers used for Data Formatting.
Table 6-4. Data Formatting (Sheet 1 of 2) Register COM10[1:0] COM10[3] COM7[2] Address 0x15 0x15 0x12 High: Negative High: Negative 0: YUV 1: RGB 00: 01: 10: 11: YVYU YUYV
VYUY
Function HSYNC/VSYNC Polarity HREF Polarity YUV Formatting
Note
YUV Sequence Exchange Output Data MSB/LSB Swap Enable D[9:0] - PCLK Reference Edge ITU-656 Format Enable
TSLB[3:2]
0x3A
UYVY
COM3[6] COM10[4] COM1[6]
0x0C 0x15 0x04
8-bits: D[9:2] 10-bits: D[9:0] 0: 1: Data update at falling edge Data update at rising edge
High: Enable 00: 01: 10: 11: SXGA VGA 0x10 to 0xF0 0x10 to 0xF0 0x01 to 0xFE 0x00 to 0xFF LSB: 1/1520 Line Period increase LSB: 1/1600 Line Period increase LSB: 1/1600 Line Period increase LSB: 1/1600 Line Period increase LSB: 1/1040 Line Period increase LSB: 1/1040 Line Period increase LSB: 1/1040 Line Period increase LSB: 1/1050 Frame Period increase LSB: 1/500 Frame Period increase LSB: 1/250 Frame Period increase LSB: 1/250 Frame Period increase LSB: 1/384 Frame Period increase LSB: 1/192 Frame Period increase LSB: 1/192 Frame Period increase
Output Range
COM15[7:6]
0x40
Frame Rate Adjust Setting (by inserting dummy pixels)
QVGA EXHCH[6:4] (MSB) EXHCL[7:0] (LSB) 0x2A 0x2B QQVGA CIF QCIF QQCIF SXGA VGA
Frame Rate Adjust Setting (by inserting dummy lines)
QVGA DM_LNH[7:0] (MSB) DM_LNL[7:0] (LSB) 0x93 0x92 QQVGA CIF QCIF QQCIF
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 6-4. Data Formatting (Sheet 2 of 2) Register Address 00: 01: 10: 11: Note Frame rate does not change Minimum 1/2 frame rate Minimum 1/4 frame rate Minimum 1/8 frame rate
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ision
Function Auto Frame Rate Adjust Range Pixel Delay Select Output HSYNC on HREF Pin Enable PCLK Output Gated by HREF Enable HSYNC Rising Edge Delay HSYNC Falling Edge Delay VSYNC and HREF/DATA drop
COM11[6:5]
0x3B
PSHFT[7:0] COM10[6] COM10[5] EXHCH[1:0] (MSB) HSYST[7:0] (LSB) EXHCH[3:2] (MSB) HSYEN[7:0] (LSB) COM9[2:1]
0x1B 0x15 0x15 0x2A 0x30 0x2A 0x31 0x14 Drop over-exposure image 0: HREF 1: HSYNC 0: Free running PCLK 1: PCLK gated by HREF
6.2.1 ITU-656 Format Enable
Instead of using HREF to define each row, the ITU-656 standard inserts a 4-byte header before and after the row data. Header Footer: [FF] [00] [00] [Sync Byte] OmniVision suggests using output range control register COM15[7:6] (0x40) to limit image data range so that the image data does not contain 0x00 and 0xFF.
6.2.2 Frame Rate Adjust
The OV9650 offers three methods of frame rate adjustment using the clock prescaler (see Section 3.3.1), by inserting 'dummy' pixels in each row's output, and by inserting dummy lines in each frame output. By inserting these dummy pixels (using EXHCH[6:4] (0x2A) and EXHCL[7:0] (0x2B)), the frame rate can be changed while leaving the pixel unchanged. Dummy Pixel Number = EXHCH[6:4] (0x2A) + EXHCL[7:0] (0x2B) Refer to Table 6-4 for the number of dummy pixels that changes the frame rate. By inserting dummy lines at frame output, the user can get the same data rate and the same data read out time at one frame. Also, in low light (night mode) conditions, the user can turn on auto frame adjust to decrease the random noise and increase the sensitivity (get more exposure time). In this mode, COM11[7] (0x3B) is high. COM11[6:5] (0x3B) is used to control the frame adjust range. See Table 6-4 for details.
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Output Formatter
6.2.3 Output Data MSB/LSB Swap Enable
See Figure 6-2 for details when MSB/LSB output data swap is enabled.
Figure 6-2 MSB/LSB Output Data Swap
MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 OV9650 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 External Device LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 OV9650 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 External Device
Default 10-bit Connection
Swap 10-bit Connection
MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 OV9650
D7 D6 D5 D4 D3 D2 D1 D0
LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0
D0 D1 D2 D3 D4 D5 D6 D7
External Device
OV9650
External Device
Default 8-bit Connection
Swap 8-bit Connection
6.2.4 D[9:0] - PCLK Reference Edge
To conserve the user's memory space, the PCLK output can be gated by HREF, which defines the active video period.
PCLK
PCLK active edge negative
HREF PCLK
PCLK active edge positive
VSYNC
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7 Digital Video Port
The two bits shown in Table 7-1 are used to increase IOL/IOH drive current and can be adjusted as a function of the customer's D[9:0], HREF, VSYNC, and PCLK loading.
Table 7-1. Output Drive Current Function 1x IOL/IOH Enable 2x IOL/IOH Enable 4x IOL/IOH Enable Register COM2[1:0] COM2[1:0] COM2[1:0] Address 0x09 0x09 0x09 2b'00 2b'01 or 2b'10 2b'11 Value
8 Special Image Effects
Table 8-1. Special Image Effects Mode Normal Color Register TSLB[7:0] MANU[7:0] MANV[7:0] TSLB[1:0] MANU[7:0] MANV[7:0] TSLB[1:0] MANU[7:0] MANV[7:0] TSLB[1:0] MANU[7:0] MANV[7:0] TSLB[1:0] MANU[7:0] MANV[7:0] TSLB[1:0] MANU[7:0] MANV[7:0] TSLB[1:0] MANU[7:0] MANV[7:0] Address 0x3A 0x67 0x68 0x3A 0x67 0x68 0x3A 0x67 0x68 0x3A 0x67 0x68 0x3A 0x67 0x68 0x3A 0x67 0x68 0x3A 0x67 0x68 0x01 0x80 0x80 0x11 0x80 0x80 0x11 0x40 0xA0 0x11 0xC0 0x80 0x11 0x80 0xC0 0x11 0x40 0x40 0x21 0x80 0x80 Value
Black & White
Sepia
Blush
Reddish
Greenish
Negative
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Preview Mode to Still Image Capture Sequence
9 Preview Mode to Still Image Capture Sequence
The procedure for OV9650 preview mode to still image capture sequence for different resolution and frame rate is as follows:
1. Preview image 2. Press still image button 3. Read out sensor below register values: * Gain: Register GAIN[9:0] {VREF[7:6] (0x03), GAIN[7:0] (0x00)} * Exposure: Register AEC[15:0] {AECHM[15:10] (0xA1), AECH[9:2] (0x10), COM1[1:0] (0x04)} 4. Set sensor to still image resolution (just change a few registers that are different to preview) * Turn off sensor AGC and AEC by setting register COM8[2] and COM8[0] (0x13) to low, respectively * Calculate and set the gain {VREF[7:6] (0x03), GAIN[7:0] (0x00)} and exposure time {AECHM[15:10] (0xA1), AECH[9:2] (0x10), COM1[1:0] (0x04)} of the still image from the gain and exposure time of the preview image 5. Wait for two frames and capture the third frame 6. Set back to preview mode and turn on AGC and AEC 7. Preview image
AEC[15:0] responds to horizontal line period for each bit. Horizontal line period includes an active pixel period and a horizontal blanking period. It counts both active pixel number and blanking pixel number. So the line period will be:
* * * * * * * 1520Tp (1280+240) 800Tp (640+160) 400Tp (320+80) 400Tp ((160+40)x2) 520Tp (352+168) 260Tp (176+84) 260Tp ((88+42)x2) for SXGA for VGA: for QVGA for QQVGA for CIF for QCIF for QQCIF
where Tp depends on the frame rate.
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9.1 Exposure Time and Gain Calculation
To get the same luminance level, the product of exposure time and gain of the still image should be the same as the preview image. To reduce still image noise, always set the exposure time "high" and the gain "low". If the frame rate of the preview image is higher than that of the still image, convert as much gain as possible to exposure time. Refer to Table 4-1 for the gain calculation. The maximum exposure time AEC[15:0] = {AECHM[15:10] (0xA1), AECH[9:2] (0x10), COM1[1:0] (0x04)} is dependent on the resolution:
* * * * * * * SXGA: VGA: QVGA: QQVGA: CIF: QCIF: QQCIF: 000001 000000 000000 000000 000000 000000 000000 00000110 01111100 00111110 00111110 01011111 00101111 00101111 00 10 00 00 10 10 10 (1048) (498) (248) (248) (382) (190) (190)
10 SCCB Interface
The OmniVision Serial Camera Control Bus (SCCB) Functional Specification is available at http://www.ovt.com. The Functional Specification provides complete information for using the SCCB to control the features of an OmniVision CAMERACHIP. The OV9650 CAMERACHIP uses the SCCB protocol to control the features noted in this document via the companion backend system ASIC. The device slave addresses of the OV9650 CAMERACHIP are: 0x60 for write (7-bit address and 1-bit write) and 0x61 for read (7-bit address and 1-bit read). The first command in the SCCB transmission must be a register reset, as most registers will rely on the default value setting.
10.1 Control Functions
Table 10-1 lists the SCCB control functions.
Table 10-1. SCCB Control Functions Function Register Reset Standby Mode Enable Tri-state Enable - D[9:0] Register COM7[7] COM2[4] COM17[1] 0x12 0x09 0x42 Address
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SCCB Interface
10.1.1 Register Reset
All registers can be reset to their default values by using the RESET pin (RESET to VDD_IO) or by using the SCCB interface (see register COM7[7] (0x12)). OmniVision suggests putting the reset register setting (set register COM7 (0x12) to 0x80) at the beginning of the sensor initialization. After software reset, wait 1 ms for the next register access (there is no limitation for other register settings).
10.1.2 Standby Mode Enable
The OV9650 CAMERACHIP can be placed in Standby mode by using the PWDN pin (PWDN to VDD_IO) or by using the SCCB interface (see register COM2[4] (0x09)). Note that using the PWDN pin results in lower Standby current (see Electrical Characteristics in the OV9650 Datasheet). Setting register OFON[3] (0x39) to high before standby can reduce the current a little bit. 10.1.2.1 Standby Mode Using the PWDN Pin Internal device clock is halted and all internal counters are reset to their default values and all SCCB registers remain unchanged. 10.1.2.2 Standby Mode Using the SCCB Interface Suspends internal circuit activity but does not halt the device clock.
10.1.3 Tri-state Enable
This bit control will immediately tri-state the data outputs. However, all internal signals will continue to be generated and transfer to the output as if it were active. It is the user's responsibility to ensure that the tri-state command is used after all functions have completed their operation. If the device is put into Standby mode, all outputs, including data and clock, are automatically tri-stated.
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10.2 Register Set
Table 10-2 provides a list and description of the Device Control registers contained in the OV9650. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses for the OV9650 are 0x60 for write and 0x61 for read. For factory-recommended settings, contact your local OmniVision FAE.
Note: All registers shown as reserved have no function or are very sensitive analog circuit references. Use OmniVision reference values (not default values).
Table 10-2.
Address (Hex) 00
Device Control Register List
Default (Hex) 00 R/W RW Description AGC[7:0] - Gain control gain setting * Range: [00] to [FF] AWB - Blue channel gain setting * Range: [00] to [FF] AWB - Red channel gain setting * Range: [00] to [FF] Vertical Frame Control
Register Name GAIN
01
BLUE
80
RW
02
RED
80
RW
03
VREF
12
RW
Bit[7:6]: Bit[5:3]: Bit[2:0]:
AGC[9:8] (see register GAIN for AGC[7:0]) VREF end low 3 bits (high 8 bits at VSTOP[7:0] VREF start low 3 bits (high 8 bits at VSTRT[7:0]
Common Control 1 Bit[7]: Bit[6]: Bit[5]: Reserved CCIR656 format QQVGA or QQCIF format. Effective only when QVGA (register bit COM7[4]) or QCIF (register bit COM7[3]) output is selected and related HREF skip option based on format is selected (register COM1[3:2]) Reserved HREF skip option 00: No skip 01: YUV/RGB skip every other row for YUV/RGB, skip 2 rows for every 4 rows for Raw data 1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows for every 8 rows for Raw data AEC low 2 LSB (see registers AECHM for AEC[15:10] and AECH for AEC[9:2])
04
COM1
00
RW
Bit[4]: Bit[3:2]:
Bit[1:0]:
05 06 07
BAVE GEAVE RSVD
00 00 00
RW RW -
U/B Average Level Automatically updated based on chip output format Y/Ge Average Level Automatically updated based on chip output format Reserved
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SCCB Interface
Table 10-2.
Address (Hex) 08
Device Control Register List (Continued)
Default (Hex) 00 R/W RW Description V/R Average Level Automatically updated based on chip output format Common Control 2 Bit[7:5]: Bit[4]: Bit[3:2]: Bit[1:0]: Reserved Soft sleep mode Reserved Output drive capability 00: 1x 01: 2x 10: 3x 11: 4x
Register Name RAVE
09
COM2
01
RW
0A 0B
PID VER
96 52
R R
Product ID Number MSB (Read only) Product ID Number LSB (Read only) Common Control 3 Bit[7]: Bit[6]: Bit[5:4]: Bit[3]: Reserved Output data MSB and LSB swap Reserved Pin selection 1: Change RESET pin to EXPST_B (frame exposure mode timing) and change PWDN pin to FREX (frame exposure enable) VarioPixel for VGA, CIF, QVGA, QCIF, QQVGA, and QQCIF Reserved Single frame output (used for Frame Exposure mode only)
0C
COM3
00
RW
Bit[2]: Bit[1]: Bit[0]:
Common Control 4 Bit[7]: Bit[6:3]: Bit[2]: 0D COM4 00 RW Bit[1]: VarioPixel for QVGA, QCIF, QQVGA, and QQCIF Reserved Tri-state option for output clock at power-down period 0: Tri-state at this period 1: No tri-state at this period Tri-state option for output data at power-down period 0: Tri-state at this period 1: No tri-state at this period Reserved
Bit[0]:
Common Control 5 Bit[7]: 0E COM5 01 RW Bit[6:5]: Bit[4]: System clock selection. If the system clock is 48 MHz, this bit should be set to high to get 15 fps for YUV or RGB Reserved Slam mode enable 0: Master mode 1: Slam mode (used for slave mode) Reserved
Bit[3:0]:
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 10-2.
Address (Hex)
Omni
ision
Device Control Register List (Continued)
Default (Hex) R/W Common Control 6 Bit[7]: Output of optical black line option 0: Disable HREF at optical black 1: Enable HREF at optical black Reserved Enable bias for ADBLC ADBLC offset 0: Use 4-channel ADBLC 1: Use 2-channel ADBLC Reset all timing when format changes Enable ADBLC option Description
Register Name
0F
COM6
43
RW
Bit[6:4]: Bit[3]: Bit[2]:
Bit[1]: Bit[0]: 10 AECH 40 RW
Exposure Value Bit[7:0]: AEC[9:2] (see registers AECHM for AEC[15:10] and COM1 for AEC[1:0])
Data Format and Internal Clock Bit[7]: Digital PLL option 0: Disable double clock option, meaning the maximum PCLK can be as high as half input clock 1: Enable double clock option, meaning the maximum PCLK can be as high as input clock Use input clock directly (no clock pre-scale available) Internal clock pre-scalar F(internal clock) = F(input clock)/(Bit[5:0]+1) * Range: [0 0000] to [1 1111]
11
CLKRC
00
RW Bit[6]: Bit[5:0]:
Common Control 7 Bit[7]: SCCB Register Reset 0: No change 1: Resets all registers to default values Output format - VGA selection Output format - CIF selection Output format - QVGA selection Output format - QCIF selection Output format - RGB selection Reserved Output format - Raw RGB (COM7[2] must be set high)
12
COM7
00
RW
Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]:
Common Control 8 Bit[7]: Bit[6]: Enable fast AGC/AEC algorithm AEC - Step size limit (used only in fast condition and COM5[0] is low) 0: Fast condition change maximum step is VSYNC 1: Unlimited step size Banding filter ON/OFF Reserved AGC Enable AWB Enable AEC Enable
13
COM8
8F
RW Bit[5]: Bit[4:3]: Bit[2]: Bit[1]: Bit[0]:
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ision
SCCB Interface
Table 10-2.
Address (Hex)
Device Control Register List (Continued)
Default (Hex) R/W Common Control 9 Bit[7]: Bit[6:4]: Reserved Automatic Gain Ceiling - maximum AGC value 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x Exposure timing can be less than limit of banding filter when light is too strong Data format - VSYNC drop option 0: VSYNC always exists 1: VSYNC will drop when frame data drops Enable drop frame when AEC step is larger than the Exposure Gap Freeze AGC/AEC Description
Register Name
14
COM9
4A
RW Bit[3]: Bit[2]:
Bit[1]: Bit[0]:
Common Control 10 Bit[7]: Set pin definition 1: Set RESET to SLHS (slave mode horizontal sync) and set PWDN to SLVS (slave mode vertical sync) HREF changes to HSYNC PCLK output option 0: PCLK always output 1: No PCLK output when HREF is low PCLK reverse HREF reverse Reserved VSYNC negative HSYNC negative
Bit[6]: Bit[5]: 15 COM10 00 RW Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: 16 17 18 19 1A RSVD HSTART HSTOP VSTRT VSTOP 00 1A BA 01 81 - RW RW RW RW Reserved
Output Format - Horizontal Frame (HREF column) start high 8-bit (low 3 bits are at HREF[2:0]) Output Format - Horizontal Frame (HREF column) end high 8-bit (low 3 bits are at HREF[5:3]) Output Format - Vertical Frame (row) start high 8-bit (low 3 bits are at VREF[2:0]) Output Format - Vertical Frame (row) end high 8-bit (low 3 bits are at VREF[5:3]) Data Format - Pixel Delay Select (delays timing of the D[9:0] data relative to HREF in pixel units) * Range: [00] (no delay) to [FF] (256 pixel delay which accounts for whole array) Manufacturer ID Byte - High (Read only = 0x7F)
1B
PSHFT
00
RW
1C
MIDH
7F
R
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 10-2.
Address (Hex) 1D
Omni
ision
Device Control Register List (Continued)
Default (Hex) A2 R/W R Manufacturer ID Byte - Low Mirror/VFlip Enable Bit[7:6]: Bit[5]: Reserved Mirror 0: Normal image 1: Mirror image VFlip enable 0: VFlip disable 1: VFlip enable Reserved Description (Read only = 0xA2)
Register Name MIDL
1E
MVFP
00
RW Bit[4]:
Bit[3:0]: 1F LAEC 00 RW Reserved
B Channel ADBLC Result Bit[7]: 20 BOS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range (high 7 bits)
Gb channel ADBLC result Bit[7]: 21 GBOS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
Gr channel ADBLC result Bit[7]: 22 GROS 80 RW Bit[6:0]: Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
R channel ADBLC result Bit[7]: 23 ROS 80 RW Bit[6:0]: 24 25 26 AEW AEB VPT 78 68 D4 RW RW RW Offset adjustment sign 0: Add offset 1: Subtract offset Offset value of 10-bit range
AGC/AEC - Stable Operating Region (Upper Limit) AGC/AEC - Stable Operating Region (Lower Limit) AGC/AEC Fast Mode Operating Region Bit[7:4]: Bit[3:0]: High nibble of upper limit High nibble of lower limit
B Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]: 27 BBIAS 80 RW Bit[6:0]: Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
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ision
SCCB Interface
Table 10-2.
Address (Hex)
Device Control Register List (Continued)
Default (Hex) R/W Description Gb Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]:
Register Name
28
GbBIAS
80
RW Bit[6:0]:
Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
Analog BLC and Regulator Control 29 Gr_COM 00 RW Bit[7:6]: Bit[5]: Bit[4]: Bit[3:0]: Reserved Bypass Analog BLC Bypass regulator Reserved
Dummy Pixel Insert MSB 2A EXHCH 00 RW Bit[7]: Bit[6:4]: Bit[3:2]: Bit[1:0]: Reserved 3 MSB for dummy pixel insert in horizontal direction HSYNC falling edge delay 2 MSB HSYNC rising edge delay 2 MSB
2B
EXHCL
00
RW
Dummy Pixel Insert LSB 8 LSB for dummy pixel insert in horizontal direction R Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]:
2C
RBIAS
80
RW Bit[6:0]:
Bias adjustment sign 0: Add bias 1: Subtract bias Bias value of 10-bit range
2D 2E 2F 30 31
ADVFL ADVFH YAVE HSYST HSYEN
00 00 00 08 30
RW RW RW RW RW
LSB of insert dummy lines in vertical direction (1 bit equals 1 line) MSB of insert dummy lines in vertical direction Y/G Channel Average Value HSYNC Rising Edge Delay (low 8 bits) HSYNC Falling Edge Delay (low 8 bits) HREF Control
32
HREF
A4
RW
Bit[7:6]: Bit[5:3]: Bit[2:0]: Bit[7:0]: Bit[7:0]: Reserved Bit[7:0]: Bit[7:0]: Bit[7:4]: Bit[3]: Bit[2:0]:
HREF edge offset to data output HREF end 3 LSB (high 8 MSB at register HSTOP) HREF start 3 LSB (high 8 MSB at register HSTART) Reserved Reserved
33 34 35-36 37 38
CHLF ARBLM RSVD ADC ACOM
00 03 XX 04 12
RW RW - RW RW
Reserved Reserved Reserved Line buffer power down - must be set to "1" before chip power down Reserved 47
39
OFON
00
RW
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 10-2.
Address (Hex)
Omni
ision
Device Control Register List (Continued)
Default (Hex) R/W Line Buffer Test Option Bit[7:6]: Bit[5]: Bit[4]: Reserved Bit-wise reverse UV output value 0: Use normal UV output 1: Use fixed UV value set in registers MANU and MANV as UV output instead of chip output Output sequence is Y U Y V instead of U Y V Y 00: Y U Y V 01: Y V Y U 10: V Y U Y 11: U Y V Y Reserved Digital BLC enable 0: Disable 1: Enable Description
Register Name
3A
TSLB
0C
RW
Bit[3:2]:
Bit[1]: Bit[0]:
Common Control 11 Bit[7]: Night mode 0: Night mode disable 1: Night mode enable - If the AGC gain goes over 2, then AGC gain drops to 0 and frame rate changes by half. COM11[6:5] limits the minimum frame rate. Also, ADVFL and ADVFL will be automatically updated. Night mode insert frame option 00: Normal frame rate 01: 1/2 frame rate 10: 1/4 frame rate 11: 1/8 frame rate Average calculation window option 00: Use full frame 01: Use half frame 10: Use quarter frame 11: Not allowed Reserved Manual banding filter enable
Bit[6:5]: 3B COM11 00 RW Bit[4:3]:
Bit[2:1]: Bit[0]:
Common Control 12 Bit[7]: 3C COM12 40 RW Bit[6:3]: Bit[2]: Bit[1:0]: HREF option 0: No HREF when VREF is low 1: Always has HREF Reserved Enable UV average Reserved
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ision
SCCB Interface
Table 10-2.
Address (Hex)
Device Control Register List (Continued)
Default (Hex) R/W Common Control 13 Bit[7:6]: Gamma selection for signal 00: No gamma function 01: Gamma used for Y channel only 10: Gamma used for Raw data before interpolation 11: Not allowed Reserved Enable color matrix for RGB or YUV Enable Y channel delay option 0: Delay UV channel 1: Delay Y channel Output Y/UV delay Description
Register Name
3D
COM13
99
RW
Bit[5]: Bit[4]: Bit[3]:
Bit[2:0]:
Common Control 14 Bit[7:2]: Bit[1]: 3E COM14 0E RW Bit[0]: Reserved Enable edge enhancement for YUV output (effective only for YUV/RGB, no use for Raw data) Edge enhancement option 0: Edge enhancement factor = EDGE[3:0] 1: Edge enhancement factor = 2 x EDGE[3:0]
Edge Enhancement Adjustment 3F EDGE 88 RW Bit[7:4]: Bit[3:0]: Edge enhancement threshold[3:0] (see register COM22[7:6} for Edge threshold[5:4]) Edge enhancement factor
Common Control 15 Bit[7:6]: Data format - output full range enable 0x: Output range: [10] to [F0] 10: Output range: [01] to [FE] 11: Output range: [00] to [FF] RGB 555/565 option (must set COM7[2] high) x0: Normal RGB output 01: RGB 565 11: RGB 555 Swap R/B in RGB565/RGB555 format Reserved
40
COM15
C0
RW
Bit[5:4]:
Bit[3]: Bit[2:0]:
Common Control 16 41 COM16 10 RW Bit[7:2]: Bit[1]: Bit[0]: Reserved Color matrix coefficient double option Reserved
Common Control 17 Bit[7:3]: Bit[2]: Bit[1]: Bit[0]: Reserved Select single frame out Tri-state output after single frame out Banding Filter Value selection 0: Use Banding Filter Value stored in register BD60ST 1: Use Banding Filter Value stored in register BD50ST
42
COM17
08
RW
Version 1.1, December 7, 2004
Proprietary to OmniVision Technologies
49
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 10-2.
Address (Hex) 43-4E 4F 50 51 52 53 54 55 56 57 58 59-61 62
Omni
ision
Device Control Register List (Continued)
Default (Hex) XX 58 48 10 28 48 70 40 40 40 0F XX 00 R/W - RW RW RW RW RW RW RW RW RW RW - RW Reserved Matrix Coefficient 1 Matrix Coefficient 2 Matrix Coefficient 3 Matrix Coefficient 4 Matrix Coefficient 5 Matrix Coefficient 6 Matrix Coefficient 7 Matrix Coefficient 8 Matrix Coefficient 9 Matrix Coefficient Sign for coefficient 9 to 2 Description
Register Name RSVD MTX1 MTX2 MTX3 MTX4 MTX5 MTX6 MTX7 MTX8 MTX9 MTXS RSVD LCC1
0: Plus 1: Minus Reserved Lens Correction Option 1 Bit[7]: Bit[6:0]: Direction of offset on X-axis Offset value
Lens Correction Option 2 63 64 65 LCC2 LCC3 LCC4 00 10 80 RW RW RW Bit[7]: Bit[6:0]: Direction of offset on Y-axis Offset value
Lens Correction Option 3 Lens Correction Option 4 Lens Correction Control Bit[7:3]: Bit[2]: Reserved Lens correction control select 0: Use LCC3 for Red, Green, and Blue channel control (LCCFB and LCCFR are not used) 1: Use LCC3 for Green channel control, LCCFB for Blue channel control and LCCFR for Red channel control Reserved Lens correction enable
66
LCC5
00
RW
Bit[1]: Bit[0]: 67 68 MANU MANV 80 80 RW RW
Manual U Value (effective only when register TSLB[4] is high) Manual V Value (effective only when register TSLB[4] is high) Manual Banding Filter MSB
69
HV
00
RW
Bit[7:6]: Bit[5:4]: Bit[3:1]: Bit[0]:
B channel pre-gain R channel pre-gain Reserved Matrix coefficient 1 sign
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ision
SCCB Interface
Table 10-2.
Address (Hex) 6A 6B 6C-7B 7C-8A 8B
Device Control Register List (Continued)
Default (Hex) 00 0A XX XX 04 R/W RW RW RW RW RW Description Manual Banding Filter Value (effective only when COM11[0] is high). Bit[7:0]: Gamma curve Gamma curve Common Control 21 Bit[7:0]: Reserved Reserved
Register Name MBD DBLV GSP GST COM21
Common Control 22 Bit[7:6]: 8C COM22 00 RW Bit[5]: Bit[4:2]: Bit[1]: Bit[0]: Edge enhancement threshold[5:4] (see register EDGE[7:4} for Edge threshold[3:0]) De-noise enable Reserved White-pixel erase enable White-pixel erase option
Common Control 23 Bit[7:5]: Bit[4]: Bit[3:2]: Bit[1]: Bit[0]: Reserved Color bar test mode Reserved Digital color gain enable Reserved
8D
COM23
00
RW
8E
COM24
00
RW
Common Control 24 Bit[7:0]: Reserved
Digital BLC Offset Sign Bit[7:4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved Digital BLC B offset sign Digital BLC R offset sign Digital BLC Gb offset sign Digital BLC Gr offset sign
8F
DBLC1
0F
RW
90
DBLC_B
00
RW
Digital BLC B Channel Offset Value Bit[7:0]: Digital BLC B channel offset value
91
DBLC_R
00
RW
Digital BLC R Channel Offset Value Bit[7:0]: Digital BLC R channel offset value
92
DM_LNL
00
RW
Dummy Line low 8 bits Bit[7:0]: Control insert Dummy line[7:0]
93 94-9C 9D 9E
DM_LNH RSVD LCCFB LCCFR
00 XX 00 00
RW - RW RW
Dummy Line high 8 bits Bit[7:0]: Reserved Lens Correction B Channel Control (if LCC3[2] = 1) Lens Correction R Channel Control (if LCC3[2] = 1) Control insert Dummy line[15:8]
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM Table 10-2.
Address (Hex) 9F
Omni
ision
Device Control Register List (Continued)
Default (Hex) 00 R/W RW Description Digital BLC Gb Channel Offset Value Bit[7:0]: Digital BLC Gb channel offset value
Register Name DBLC_Gb
A0
DBLC_Gr
00
RW
Digital BLC Gr Channel Offset Value Bit[7:0]: Digital BLC Gr channel offset value
Exposure Value - AEC MSB 6 bits A1 AECHM 40 RW Bit[7:6]: Bit[5:0]: Reserved AEC[15:10] (see registers AECH for AEC[9:2] and COM1 for AEC[1:0])
A2 A3 A4
BD50ST BD60ST COM25
9D 83 00
RW RW RW
Banding Filter Value (effective only when COM11[0] is low and COM17[0] is high) Banding Filter Value (effective only when COM11[0] is low and COM17[0] is low) Common Control 25 Bit[7:0]: Reserved
A5 A6 A7 A8-AA
COM26 G_GAIN VGA_ST ACOM
00 80 14 XX
RW RW RW -
Common Control 26 Bit[7:0]: Reserved Reserved Reserved Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
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ision
Prototyping and Evaluation Modules
11 Prototyping and Evaluation Modules
OmniVision Technologies Inc. supplies prototyping and evaluation modules to demonstrate operation of the associated CAMERACHIP products, as well as to demonstrate associated companion backend processor, where required.
11.1 OV9650EAA Prototyping Module
The OV9650EAA prototyping module is used for general design-in and evaluation purposes. The module provides a simple 32-pin header-connector interface to the relevant I/O and control registers in the OV9650 CAMERACHIP. The module includes the necessary sensor, lens/holder, a few capacitors, and resistors. The OV9650EAA prototyping module can be directly connected to any companion backend processor solution or system interface. The header-connector interface allows for access to the 10-bit digital output data, PCLK, vertical sync, horizontal sync and SCCB signals. The backend interface can use the Serial Camera Control Bus (SCCB) interface software to adjust the control register values.
11.2 OV9650ECX USB 2.0 Evaluation Module
The OV9650ECX USB2.0 evaluation module is provided so that potential customers may evaluate both the live video function of the CAMERACHIP as well as the SCCB control interface software. The OV9650 CAMERACHIP output is a RGB raw data or YUV stream connected to a USB 2.0 controller operating at a high-speed bus data rate (480 Mbps). Using a high performance computer system with a USB 2.0 host (cannot guarantee for every system), the OV9650 USB module will stream video in SXGA format (1280x1028 at 15 fps), VGA format (640x480 at 30 fps) or in QVGA format (320x240 at 60 fps). This configuration requires a Windows(R) 2000 or XP operating system. Additionally, the SCCB software allows the evaluator to adjust the image characteristics in real-time.
12 Lens selection
The OV9650 is a quarter-inch format CAMERACHIP that is compatible with numerous lenses in the market. The key considerations in lens selection are lens quality and resultant cost. OmniVision Technologies, Inc. has qualified several lens suppliers for the various formats, sizes, and quality of lenses available. OmniVision has developed a Lens Supplier Partner List to complement our CAMERACHIP products. This listing is available at http://www.ovt.com on the Partners page. Contact your local OmniVision FAE for recommended OV9650 lenses.
13 OV9650 Bug List
None as of this revision.
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM
Omni
ision
Appendix A Reference SCCB Settings
Contact your local OmniVision FAE for updated reference register settings.
54
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ision
OV9650 Bug List
Note:
* All information shown herein is current as of the revision and publication date. Please contact OmniVision to obtain the current version of this documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `CameraChip', and `OmniPixel' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. 1341 Orleans Drive Sunnyvale, CA USA (408) 542-3000
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OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChipTM
Omni
ision
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